1. Field of the Invention
The present invention generally relates to microelectronic structures, and more particularly to through silicon vias (TSVs), and even more preferably to the formation of TSVs connected to conducting structures.
2. Background and Description of Related Art
In the past, microelectronic devices, including integrated circuits (ICs), have increased performance by shrinking device features, thereby creating a higher density of circuits on a substrate. To continue the quest for increased performance, in additional the described two-dimensional (2D) shrinking, manufactures are stacking substrates to gain density in a third dimension (i.e. 3D-ICs). To enable the 3D efforts, TSVs are used to connect a first substrate to bond pads, interposers, redistribution layers, a second substrate, or other conductive features.
TSVs extend from within an integrated circuit built on/in a first substrate to the backside of the first substrate. Initially, the TSVs end within the substrate. The substrate is thinned to expose the TSVs so they may subsequently be connected to the bond pads, interposer, redistribution layer, second substrate or the like. However, during the thinning/exposure process(es) the substrate may form a fissure or break. This is particularly true if the TSVs are different heights. And even if the substrate is not damaged, the current process and resulting structure are prone to shorting or leakage.
Therefore, a robust process is needed to accommodate TSVs of varying heights. This invention provides a novel process and resulting structure to accommodate TSVs of varying heights and is also applicable to TSVs having uniform heights.